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the A4409 is a power management ic that uses a buck or buck-boost pre-regulator to efficiently convert automotive battery voltages into a tightly regulated intermediate voltage, complete with control, diagnostics, and protections. the output of the pre-regulator supplies a 5 v, 300 ma min ldo and a 5 v, 200 ma min ldo. designed to supply can or microprocessor power supplies in high-temperature environments, the A4409 is ideal for underhood applications. enable-input to the A4409 is compatible to a high-voltage battery level (enbat). diagnostic outputs from the A4409 include a power-on-reset output (npor) with a fixed 22.5 ms typical delay. dual bandgaps, one for regulation and one for fault checking, improve long-term reliability of a system designed around the A4409. the A4409 contains a window watchdog timer that can be programmed to accept a wide range of clock frequencies (wd adj ). the watchdog timer has a fixed 30 ms activation delay to accommodate processor startup. the watchdog timer has an enable/disable pin (active low, wd enn ) to facilitate initial factory programming or field reflash programming. A4409-ds, rev. 4 ? automotive aec-q100 qualified ? v in operating range from 3 to 36 v, with 40 v maximum ? buck or buck-boost pre-regulator (vreg) ? adjustable pwm switching frequency: 250 khz to 2.4 mhz ? pwm frequency can be synchronized to external clock ? two 5 v internal ldo regulators with foldback short- circuit protection ? power-on reset (npor) with fixed delay of 22.5 ms ? programmable window watchdog timer with a fixed activation delay of 30 ms ? active low, watchdog timer enable/disable pin (wd enn ) ? dual bandgaps for increased reliability: bg1 for vreg, 5v0, and vcp reference bg2 for v5 reference, and vreg, 5v0, and vcp fault detection ? ignition-enable input (enbat) ? frequency dithering helps reduce emi/emc ? undervoltage protection for all output rails ? pin-to-pin and pin-to-ground tolerant at every pin ? thermal shutdown protection ? ?40oc to 150oc junction temperature range adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor package: 20-pin etssop (suffix lp) A4409 simplifed block diagram not to scale A4409 6.6 v (vreg) buck-boost pre-regulator 5 v ldo (v5) with foldback protection 5 v ldo (5v0) with foldback protection bandgap 1 bandgap 2 charge pump thermal shutdown (tsd) npor output programmable window watchdog timer with activation delay continued on next page... features and benefits description applications provides system power for (c/dsp, can, sensors, etc.) in automototive control modules, such as: ? electronic power steering (eps) ? transmission control units (tcu) ? advanced braking systems (abs) ? emissions control modules ? other automotive applications
2 selection guide part number temp. range package packing 1 lead frame A4409klptr-t C40c to 150c 20-pin etssop with thermal pad 4000 pieces per 13-in. reel 100% matte tin 1 contact allegro for additional packing options. protection features include dual control loop for pre-regulator rail. in case of a shorted output, all linear regulators feature foldback overcurrent protection. the switching regulator includes pulse- by-pulse current limit, hiccup mode short-circuit protection, lx short-circuit protection, missing asynchronous diode protection, and thermal shutdown. the A4409 is supplied in a low-profile (1.2 mm maximum height), 20-lead etssop package (suffix lp) with exposed thermal pad. description (continued) absolute maximum ratings 1 characteristic symbol notes rating unit vin pin v in ?0.3 to 40 v enbat pin v enbat ?0.3 to 8 v with current limiting resistor 2 ?13 to 40 v i enbat 75 ma lx pin v lx ?0.3 to v in + 0.3 v t < 250 ns ?1.5 v t < 50 ns v in + 3 v vcp, cp1, and cp2 pins v vcp , v cpx ?0.3 to 50 v all other pins ?0.3 to 7.5 v junction temperature t j ?40 to 150 oc storage temperature range t s ?55 to 150 oc 1 stresses beyond those listed in this table may cause permanent damage to the device. the absolute maximum ratings are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the electrical characteristics table is not implied. exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2 the higher enbat ratings (-13 v and 40 v) are measured at node a in the following circuit confguration: + - node ?a? 450 v enbat enbat gnd A4409 thermal characteristics : may require derating at maximum conditions; see application information characteristic symbol test conditions* value unit junction-to-ambient thermal resistance r jc etssop-20 (lp) package 32 oc/w *additional thermal information available on the allegro website. specifications adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
3 vin vcc comp fset/sync npor e nbat wd adj wd in wd enn pgnd gnd v5 5v0 vldo v reg lg lx vcp cp1 cp2 ldo bg1 bg2 osc2 osc1 tsd soft star t t ss 5v0 uv 5v ldo 5v ldo wd osc o ne shot t wd(fault) window watchdog timer (wwdt) charge pump startup / shutdown sequence master ic por * indicates a latched fault npor timing deglitch t d (enbat,filt ) deglitch t d(filt) falling delay t d(off)ldo buck-boost p re-regulator (vreg) with hiccup mode stop pwm fb2 fb1 connect lg to vcc for buck only mode bg1 bg2 ldos on bg2 5v0 uv 5v0 foldback foldback ss ok v reg_ov bg1_uv bg2_uv vin_uv vcp ov *d1 missing *i l x(lim) mpor clk 1mhz wd start wd fault 5v0 uv *d1 missing *i lx(lim) v reg on ldos on on en mpor 5v0 uv v reg_ok + ? wd clk wd fault clk 1mhz a440 9 en on wd start wd enn = 0 or open enables wd 60 k 650 k 0.1 f 3.3 k 3.3 v typ 2.6 v typ 13 k t wdto(slow) = 4 ms t wdto(fast) = 0.5 ms wd enn clk in npor 5v0 8.66 k 100 na 17.4 k 3.3 nf 10 pf 1 f sync (optional) key_sw vba t d in 0.1 f 0603 2 4.7 f 50 v 1210 50-100 f 50 v en v reg bg2 bg1 bg1 bg2 bg2_uv bg1_uv comp bg1 bg2 v reg on v cp uv vcp uv/ov clk 1mhz clk @ f osc 2.2 f 1 f 0.1 a 75 m d1 1 2 k q1 d2 6.6 v 250 ma 4 10 f 16 v / x7r / 1206 l1 6.8 h 60 m typ r emove d2 and q1 for buck only mode 2.2 f 2.2 f 2.2 f 5 v 300 ma 5 v 200 ma functional block diagram / typical schematic buck-boost mode (f osc = 2 mhz) adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
4 terminal list table number name function 1 vcp charge pump reservoir capacitor 2 vin input voltage 3 enbat ignition-enable input from the key/switch through a 1 k resistor 4 gnd ground 5 vcc internal voltage regulator bypass capacitor pin 6 comp error amplifier compensation network pin for the buck-boost pre-regulator 7 fset/ sync frequency setting and synchronization input 8 npor active low, open-drain regulator fault detection output 9 wd enn watchdog enable pin: open/low C wd is enabled, high C wd is disabled 10 wd in watchdog refresh input (rising edge triggered) from a microcontroller or dsp 11 5v0 5 v , 300 ma regulator output 12 v5 5 v , 200 ma regulator output 13 wd adj the watchdog window time is programmed by connecting r adj from this pin to ground 14 vldo input for the ldos 15 vreg feeback pin for vreg output, connect to vreg converter output capacitors 16 lg boost gate drive output for the buck-boost pre-regulator 17 pgnd power ground 18 lx switching node for the buck-boost pre-regulator 19 cp1 charge pump capacitor connection 20 cp2 charge pump capacitor connection C pad 1 2 3 4 5 11 12 13 14 15 6 7 8 9 10 16 17 18 19 20 npor wd enn wd in 5v0 v5 wd ad j vldo vreg lg pa d pgnd lx cp1 cp2 vcp vin enbat gnd vcc comp fset/sync package lp, 20-pin etssop pinout diagram adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
5 characteristic symbol test conditions min. typ. max. unit general specifications operating input voltage v in after v in > v in(start) , v enbat 4 v, buck-boost pre-regulator 3 13.5 36 v after v in > v in(start) , v enbat 4 v, buck pre- regulator 5.5 13.5 36 v vin uvlo start v in(start) v in rising ? ? 5 v vin uvlo stop v in(stop) v in falling, when in buck-boost mode ? ? 2.9 v supply quiescent current 1 i q v in = 13.5 v, v enbat 4 v, no load on vreg C 10 C ma i q(sleep) v in = 13.5 v, v enbat 2 v, no load on vreg C C 10 a pwm switching frequency and dithering switching frequency f osc r fset = 8.66 k? 1.8 2 2.2 mhz r fset = 57.6 k? 343 400 457 khz frequency divide by 2 start 2 v in(freq/2,start) v in rising, frequency = f osc /2 18 19 20 v frequency divide by 2 stop 2 v in(freq/2,stop) v in falling, frequency = f osc /2 17 18 19 v frequency dithering f osc as a percent of f osc C 12 C % vin dithering start threshold v in(dither,on) low range, v in rising 9 9.5 10 v high range, v in falling 17 18 19 v vin dithering stop threshold v in(dither,off) low range, v in falling 8.5 9 9.5 v high range, v in rising 18 19 20 v vin dithering hysteresis v in(dither,hys) C 500 C mv charge pump (vcp) output voltage v vcp v vcp C v in 4.1 6.6 C v switching frequency f sw(cp) C 65 C khz vcc output output voltage v vcc v vreg = 6.6 v C 4.6 C v thermal protection thermal shutdown threshold 2 t tsd t j rising 160 170 180 oc thermal shutdown hysteresis 2 t hys C 20 C oc 1 negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. electrical characteristics C general specifications 1 : valid at 3 v v in 36 v in buck-boost mode and v in having frst reached v in(start) , C40oc t a = t j 150oc, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
6 characteristic symbol test conditions min. typ. max. unit output voltage specifications pre-regulator output voltage C vreg regulating v vreg v in = 13.5 v, enbat = 1, 0.1 a i vreg 1 a 6.47 6.6 6.7 v pre-regulator output voltage C vldo regulating v vldo(reg) vreg pin open, measured at vldo pin, v in = 13.5 v, enbat = 1, 0.1 a i vreg 1 a 5.88 6 6.12 v pulse width modulation (pwm) pwm ramp of fset v pwmoffset v comp for 0% duty cycle C 400 C mv lx rising slew rate 2 sr lx(rise) v in = 13.5 v, 10% to 90%, i vreg = 1 a C 1.7 C v/ns lx falling slew rate 2 sr lx(fall) v in = 13.5 v, 10% to 90%, i vreg = 1 a C 1.5 C v/ns buck minimum on-time 2 t on(buck,min) C 85 160 ns buck minimum off-time t off(buck,min) C 0 C ns buck maximum duty cycle d buck(max) C 100 C % boost minimum on-time t on(boost,min) C 60 120 ns boost maximum duty cycle d boost(max) v in = 3.5 v C 70 C % comp to lx current gain g m(power) C 4.5 C a/v slope compensation 2 s e f osc = 2 mhz 3.84 4.8 5.76 a/s f osc = 400 khz 0.76 0.96 1.16 a/s internal mosfet mosfet on resistance r ds(on) v in = 13.5 v, t j = ?40c 2 , i ds = 0.1 a C 60 75 m? v in = 13.5 v, t j = 25c 2 , i ds = 0.1 a C 80 100 m? v in = 13.5 v, t j = 150c, i ds = 0.1 a C 140 170 m? mosfet leakage i fet(leak) v enbat 2 v, v lx = 0 v, v in = 13.5 v, ?40c t j 85c 2 C C 10 a v enbat 2 v, v lx = 0 v, v in = 13.5 v, ?40c t j 125c 2 C C 100 a v enbat 2 v, v lx = 0 v, v in = 13.5 v, ?40c t j 150c C 50 150 a error amplifier open loop voltage gain a vol C 65 C db transconductance g m(ea) 550 750 950 a/v output current i o(ea) C 75 C a maximum output voltage v o(ea,max) 1.3 1.7 2.1 v minimum output voltage v o(ea,min) C C 200 mv comp pull-down resistance r comp hiccup = 1 or fault = 1 or ic disabled C 1 C k? 1 negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. electrical characteristics C buck and buck-boost pre-regulator specifications 1 : valid at 3 v v in 36 v in buck-boost mode and v in having frst reached v in(start) , C40oc t a = t j 150oc, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
7 characteristic symbol test conditions min. typ. max. unit boost mosfet (lg) gate driver lg high output voltage v lg(on) v in = 7 v, v vreg = 6.35 v 4.6 C 6.35 v lg low output voltage v lg(off) v in = 13.5 v, v vreg = 6.85 v C 0.2 0.4 v lg source current 1 i lg(on) v in = 7 v, v vreg = 6.35 v, v lg = 1 v C C500 C ma lg sink current 1 i lg(off) v in = 13.5 v, v vreg = 6.85 v, v lg = 1 v C 500 C ma lg leakage current 2 i lg(leak) v in = 13.5 v, v vreg = 6.6 v, v lg = 3 v C C 10 a soft start ss ramp time t ss(ramp) C 1 C ms ss pwm frequency foldback f sw(ss) 0 v v vreg 3.3 v, v comp = v o(ea,max) C f osc /8 C C 0 v v vreg 3.3 v C f osc /2 C C v vreg > 3.3 v C f osc C C hiccup mode hiccup ocp pwm counts t hic(ocp) v vreg < 2.4 v (typical), v comp = v o(ea,max) C 15 C pwm cycles v vreg > 2.4 v (typical), v comp = v o(ea,max) C 60 C pwm cycles hiccup mode recovery time t rec(hic) lx switching stops to lx switching starts, during vreg overcurrent C 2 C ms current protections pulse-by-pulse current limit i lim 3.6 4.1 4.6 a lx short-circuit current limit i lim(lx) 6 7 C a missing asynchronous diode (d1) protection detection level v d(open) ?1.5 ?1.3 ?0.9 v time filtering 2 t d(open) 50 C 250 ns 1 negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. electrical characteristics C buck and buck-boost pre-regulator specifications (continued) 1 : valid at 3 v v in 36 v in buck-boost mode and v in having frst reached v in(start) , C40oc t a = t j 150oc, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
8 characteristic symbol test conditions min. typ. max. unit v5 linear regulator v5 accuracy and load regulation v v5 10 ma i v5 200 ma, v vreg = 5.4 v 4.9 5 5.1 v v5 dropout v v5(dropout) i v5 = 200 ma, v vldo = 4.91 v 4.75 C C v v5 output capacitance range 2 c v5(out) 1 C 22 f v5 overcurrent protection v5 current limit 1 i v5(lim) v v5 = 5 v ?230 ?325 C ma v5 foldback current 1 i v5(fb) v v5 = 0 v ?80 ?120 ?160 ma v5 startup v5 startup time 2 t v5(start) c v5 2.9 f, load = 25 ? 5% (200 ma) C 0.24 1 ms 5v0 linear regulat or 5v0 accuracy and load regulation v 5v0 10 ma i 5v0 300 ma, v vreg = 5.4 v 4.9 5 5.1 v 5v0 dropout v 5v0(dropout) i 5v0 = 300 ma, v vldo = 4.91 v 4.75 C C v 5v0 output capacitance range 2 c 5v0(out) 1 C 22 f 5v0 overcurrent protection 5v0 current limit 1 i 5v0(lim) v 5v0 = 5 v ?345 ?485 C ma 5v0 foldback current 1 i 5v0(fb) v 5v0 = 0 v ?100 ?165 ?230 ma 5v0 startup 5v0 startup time 2 t 5v0(start) c 5v0 2.9 f, load = 20 ? 5% (250 ma) C 0.24 1 ms 1 negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. electrical characteristics C linear regulator (ldo) specifications 1 : valid at 3 v v in 36 v in buck- boost mode and v in having frst reached v in(start) , C40oc t a = t j 150oc, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
9 characteristic symbol test conditions min. typ. max. unit ignition-enable (enbat) input enbat thresholds v enbat(h) v enbat rising 2.8 3.2 3.5 v v enbat(l) v enbat falling 2.1 2.5 2.8 v enbat hysteresis v enbat(hys) v enbat(h) C v enbat(l) C 700 C mv enbat bias current 1 i ib(enbat) t j = 25c 2 , v enbat = 3.51 v C 28 45 a t j = 150c, v enbat = 3.51 v C 35 60 a enbat resistance r enbat C 650 C k enbat deglitch enable filter/deglitch time t d(enbat,filt) 10 15 20 s enbat shutdown delay ldo shutdown delay t d(off)ldo measure t d(off)ldo from the falling edge of enbat to the time when all ldos begin to decay 15 50 100 s fset/sync input fset/sync pin voltage v fset/sync no external sync signal C 800 C mv fset/sync open circuit (undercurrent) detection time t fset/sync(uc) pwm switching frequency becomes 900 khz upon detection C 3 C s fset/sync short-circuit (overcurrent) detection t ime t fset/sync(oc) pwm switching frequency becomes 900 khz disabled upon detection C 3 C s sync. high threshold v sync(h) v sync rising C C 2 v sync. low threshold v sync(l) v sync falling 0.5 C C v sync. input duty cycle d sync C C 80 % sync. input pulse width t pw(sync) 200 C C ns sync. input transition times 2 t t(sync) C 10 15 ns 1 negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. electrical characteristics C control inputs 1 : valid at 3 v v in 36 v in buck-boost mode and v in having frst reached v in(start) , C40oc t a = t j 150oc, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
10 characteristic symbol test conditions min. typ. max. unit npor undervoltage protection thresholds 5v0 undervoltage thresholds v 5v0(uv,h) v 5v0 rising C 4.665 C v v 5v0(uv,l) v 5v0 falling 4.5 4.625 4.75 v 5v0 undervoltage hysteresis v 5v0(uv,hys) v 5v0(uv,h) C v 5v0(uv,l) 20 40 60 mv npor turn-on and turn-off delays npor turn-on delay t d(on)npor 18 22.5 27 ms npor turn-off propagation delay t d(off)npor enbat low to npor low, measured after enbat deglitch time t d(enbat,filt) C C 3 s npor output voltages npor output low voltage v npor(l) enbat high, v in 2.5 v, i npor = 4 ma C 150 400 mv enbat high, v in = 1.5 v, i npor = 2 ma C C 800 mv npor leakage current 1 i npor(leak) v npor = 3.3 v C C 2 a npor undervol tage filtering/deglitch npor undervoltage filter/deglitch times t d(npor,filt) applies to undervoltage of the 5v0 voltage 10 15 20 s 1 negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). electrical characteristics C diagnostic outputs 1 : valid at 3 v v in 36 v in buck-boost mode and v in hav- ing frst reached v in(start) , C40oc t a = t j 150oc, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
11 characteristic symbol test conditions min. typ. max. unit vreg, vcp, and bg thresholds vreg overvoltage threshold v vreg(ov,h) v vreg rising, pwm disabled 6.8 6.93 7.18 v vreg overvoltage hysteresis v vreg(ov,hys) C 100 C mv vreg undervoltage thresholds v vreg(uv,h) v vreg rising 4.16 4.41 4.64 v v vreg(uv,l) v vreg falling C 4.3 C v vreg undervoltage hysteresis v vreg(uv,hys) v vreg(uv,h) C v vreg(uv,l) C 100 C mv vcp overvoltage threshold v vcp(ov,h) v vcp rising, pwm disabled 11 12.5 14 v vcp undervoltage thresholds v vcp(uv,h) v vcp rising, pwm enabled 3 3.2 3.4 v v vcp(uv,l) v vcp falling, pwm disabled C 2.7 C v vcp undervoltage hysteresis v vcp(uv,hys) v vcp(uv,h) C v vcp(uv,l) C 500 C mv bg1 and bg2 undervoltage thresholds 2 v bgx(uv) bg1 or bg2 rising 1 1.05 1.1 v undervoltage and overvoltage filtering/deglitch undervoltage filter/deglitch time t d(uv,filt) 10 15 20 s overvoltage response time 2 t d(ov,filt) C 1 C s 1 negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. electrical characteristics C diagnostic outputs (continued) 1 : valid at 3 v v in 36 v in buck-boost mode and v in having frst reached v in(start) , C40oc t a = t j 150oc, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
12 characteristic symbol test conditions min. typ. max. unit wd enable input (wd enn ) wd enn voltage thresholds v wdenn(l) v wdenn falling, wwdt enabled 0.8 C C v v wdenn(h) v wdenn rising, wwdt disabled C C 2 v wd enn input resistance r wdenn C 60 C k? wd in voltage thresholds and current wd in input voltage thresholds v wdin(l) v wdin falling, wd adj pulled low by r adj 0.8 C C v v wdin(h) v wdin rising, wd adj charging C C 2 v wd in input current 1 i wdin v wdin = 5 v ?10 1 10 a wd in timing specifications wd in frequency f wdin C C 750 hz wd in duty cycle d wdin 20 50 80 % watchdog activation delay t wd(start) 24 30 36 ms wd programming wd timeout fast range 2 t wdto(fast) 0.5 C 12.5 ms wd timeout slow range 2 t wdto(slow) 4 C 100 ms wd timeout, fast clock t wdto(fastclk) r adj = 13 k? 0.4 0.5 0.6 ms r adj = 324 k? 10 12.5 15 ms wd t imeout, slow clock t wdto(slowclk) r adj = 13 k? 3.2 4 4.8 ms r adj = 324 k? 80 100 120 ms wd one-shot time wd pulse t ime after wd fault t wd(fault) 1.6 2 2.4 ms 1 negative current is defned as coming out of the node or pin (sourcing), positive current is defned as going into the node or pin (sinking). 2 ensured by design and characterization, not production tested. electrical characteristics C window watchdog timer (wwdt) 1 : valid at 3 v v in 36 v in buck-boost mode and v in having frst reached v in(start) , C40oc t a = t j 150oc, unless otherwise specifed. adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
13 table 1: startup and shutdown logic (signal names consistent with functional block diagram) A4409 status signals supply control (0=off, 1=on) A4409 mode enbat mpor vreg uv 5v0_uv vreg on ldos on x 1 x x 0 0 reset 0 0 1 1 0 0 off 1 0 1 1 1 0 startup 1 0 0 1 1 0 1 0 0 1 1 1 1 0 0 0 1 1 run 0 0 0 0 1 1 50 s delay 0 0 0 0 1 0 shutdown 0 0 0 1 1 0 0 0 0 1 0 0 0 0 1 1 0 0 off x = dont care mpor = bg1_uv or bg2_uv or vin_uv or tsd or vcp_uv or vcp_ov or d1 missing (latched) + i lim(lx) (latched) time adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
14 table 2: summary of fault mode operation fault type and condition A4409 response to fault npor latched fault? reset method or correction 5v0 undervoltage closed loop control will try to raise the voltage but may be constrained by the foldback or pulse-by- pulse current limit low no decrease the load 5v0 overcurrent foldback current limit will reduce the output voltage transitions low if 5v0 < v 5v0(uv,l) no decrease the load v5 undervoltage closed loop control will try to raise the voltage but may be constrained by the foldback current limit not affected no decrease the load v5 overcurrent foldback current limit will reduce the output voltage not affected no decrease the load vreg pin open circuit vldo pin will take over regulation, power dissipation in ic will increase not affected no connect the vreg pin vreg shorted to ground, v vreg < 2.4 v, v comp e avo(max) continue to pwm but turn off lx when the high- side mosfet current exceeds i lim depends on 5v0 no remove the short circuit vreg overcurrent, v vreg < 2.4 v, v comp = e avo(max) enters hiccup mode after 15 ocp faults depends on 5v0 no decrease the load vreg overcurrent, v vreg > 2.4 v, v comp = e avo(max) enters hiccup mode after 60 ocp faults depends on 5v0 no decrease the load vreg asynchronous diode (d1) missing results in an mpor after 1 detection, so all regulators are of f low yes place d1 then cycle enbat or vin asynchronous diode (d1) short circuited or lx shorted to ground results in an mpor after the high-side mosfet current exceeds i lim,lx , so all regulators are off low yes remove the short then cycle enbat or vin fset/sync pin open circuit oscillator frequency becomes default frequency 900 khz not af fected no connect the fset/sync pin fset/sync pin shorted to ground oscillator frequency becomes default frequency 900 khz not af fected no remove the short circuit charge pump (vcp) overvoltage results in an mpor, so all regulators are shut off depends on 5v0 no check vcp/cp1/cp2 pins and components, then cycle enbat or vin charge pump (vcp) undervoltage results in an mpor, so all regulators are shut off depends on 5v0 no check vcp/cp1/cp2 pins and components vcp pin open circuit results in vcp_uv and an mpor, so all regulators are shut off depends on 5v0 no connect the vcp pin vcp pin shorted to ground results in high current from the charge pump and (intentional) fusing of an internal trace. also results in an mpor, so all regulators are shut off depends on 5v0 no remove the short circuit and replace the A4409 comp shorted high vreg ov,h will trip, so all regulators are shut off depends on 5v0 yes remove the high level from the comp pin then cycle enbat or vin cp1 or cp2 pin open circuit results in vcp_uv and an mpor, so all regulators are shut off depends on 5v0 no connect the cp1 or cp2 pins cp1 pin shorted to ground results in vcp_uv and an mpor, so all regulators are shut off depends on 5v0 no remove the short circuit continued on next page... adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
15 fault type and condition A4409 response to fault npor latched fault? reset method or correction cp2 pin shorted to ground results in high current from the charge pump and (intentional) fusing of an internal trace. also results in an mpor, so all regulators are shut off. depends on 5v0 no remove the short circuit and replace the A4409 bg1 or bg2 undervoltage results in an mpor, so all regulators are shut off depends on 5v0 no raise vin or wait for bgs to power up bg1 or bg2 overvoltage if bg1 is too high, 5v0 will appear to be overvoltage, because bg2 is good. if bg2 is too high, 5v0 will appear to be undervoltage, because bg1 is good. low no replace the A4409 vin undervoltage results in an mpor, so all regulators are shut off depends on 5v0 no raise vin thermal shutdown results in an mpor, so all regulators are shut off depends on 5v0 no let the A4409 cool wd adj pin shorted to ground or open circuit a wd adj fault only affects the npor output. the remainder of the A4409 operates normally. low no remove the short circuit or connect the pin table 2: summary of fault mode operation (continued) adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
16 figure 1: startup and shutdown sequence timing diagrams (not to scale) n p c o v r en lx vin 5v0 v5 p or o mp f os c / 2 r eg > v v 5v0(uv ,h) t d(ss ) bat 5v0 > v 5v0(uv,h) v in(star t, max ) v vr e t ss (ramp) t e g(uv, h) d(on)npo r t < < t d(enbat,filt ) f os c v 5v0 t d(enbat,filt ) t d(off)ld o (uv,l) l shu t be fo r 5 v t d(off)npo r t do wn sequ ence r e re -start is ac k v 0 < v 5v0(uv ,l) must fi nish k no wl edge d adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
17 5 np co v en lx vin 5.0v 5v po r om p f os c / 2 re g 13.5 v t d (ss ) ba t v vr e v 5v0(uv,h ) t ss (ramp) v 5v0(uv,l ) de c th e t d(on)npor f os c eg (u v, h) ca y ra te of the vi e total i nput ca pa ~5 .6 v @ n pin wi ll depe n ac it anc e and lo ad @ 25 oc d on ds . vi n pi n: ~6.7 v 100% duty cycl e dropout will depend on output load @ 25 oc f os c v vc c > v v vc c( st op ) figure 2: input undervoltage timing, when vin > v in(stop) adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
18 figure 3: input undervoltage timing, when vin < v in(stop) v 5. np com vr enba lx vi n .0 v 5v po r mp f osc / 2 re g 13.5 v t t d(ss) at v vreg(uv,h) v 5v0(uv,h) ss(ramp) v 5v0(uv,l) de th t d(on)npor vin pin: ~ ecay rate of the v he total input cap ~5.6 v @ 25oc 6.7 v @ 25oc vi n pin will depe pacitance and loa 100% d nd on ads. duty cycl e mpor t v in < v in(sto p) f osc t d(on)npor d(npor,filt) f osc adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
19 figure 4: vreg short circuit to ground hiccup operation * signal is internal to A4409 en _ h h c o o v r h ic * h ic * o mp o cp * lx r eg f os c v o(ea,max) f osc /8 15 oc p t rec(hic) f osc /2 f / 8 f osc / 8 15 oc p f / 2 f osc / 2 f osc /8 1 5 o c 5 c p f osc /2 f osc /8 adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
20 setting up the pre-regulator this section describes component selection for the A4409 pre- regulator, including charge-pump circuit, inductor, diodes, boost mosfet, and input and output capactors. this section also cov- ers loop compensation. charge pump capacitors the charge pump requires two capacitors: a 2.2 f capacitor con- nected from pin vcp to pin vin, and a 1 f capacitor connected between pins cp1 and cp2. these capacitors should be high quality ceramic capacitors, such as x7r, with a voltage rating of at least 50 v. pwm switching frequency when the pwm switching frequency is chosen, the designer should be aware of the minimum controllable on-time, t on(min) , of the A4409. if the systems required on-time is less than the A4409s minimum controllable on-time, then switch-node jitter will occur and the output voltage will have increased ripple or oscillations. the pwm switching frequency should be calculated using equa- tion 1, where t on(buck,min) is the minimum controllable on-time of the A4409 (160 ns typical), and v in(max) is the maximum required operational input voltage (not the peak surge voltage). f osc < 6.6 v t on(buck,min) v in(max) (1) if the A4409s synchronization function is used, then the base oscillator frequency should be chosen such that jitter will not result at the maximum synchronized switching frequency accord- ing to equation 1. r fset can be estimated using equation 2 below. r fset = 0.0455 f osc 1 (2) ? 1.98 (k) where f osc is in mhz. pre-regulator output inductor (l1) for peak current mode control, it is well known that the system will become unstable when the duty cycle is above 50% without adequate slope compensation (s e ). however, the slope compen- sation in the A4409 is a fixed value based on the oscillator fre- quency (f osc ). therefore, it is important to calculate an inductor value so the falling slope of the inductor current (s f ) will work well with the A4409s slope compensation. equation 3 can be used to calculate a range of values for the output inductor for buck or buck-boost. l1 2 ( vreg + v f ) (3) ( vreg + v f ) s e s e where v f is the asynchronous diode forward voltage, f osc is the programmed oscillator frequency in khz, and s e slope com- pensation can be calculated from equation 4 and is in amperes per microsecond (a/s). the resultant inductor value will be in microhenries (h). (4) s e = 0.24 f osc if equation 3 yields an inductor value that is not a standard value, then the next closest available value should be used. the final inductor value should allow for 10%-20% of initial tolerance and 20%-30% of inductor saturation. the inductor should not saturate given the peak operating current during overload. equation 5 calculates the current. in equation 5, v in(max) is the maximum continuous input voltage, such as 16 v, and v f is the asynchronous diodes forward voltage. (5) s e ( vreg + v f ) 0.9 f osc ( v in(max) +v f ) i peak = 4.6 a ? after an inductor is chosen, it should be tested during output overload and short-circuit conditions. the inductor current should be monitored using a current probe. a good design should ensure the inductor or the regulator is not damaged when the output is shorted to ground at maximum input voltage and the highest expected ambient temperature. inductor ripple current can be calculated using equation 6 for buck mode and equation 7 for buck-boost mode. (6) ( v in ? vreg ) vreg f sw l1 v in i l1 = (7) v in d boost f sw l1 i b / b = pre-regulator output capacitors the output capacitors filter the output voltage to provide an acceptable level of ripple voltage, and they store energy to help design and component selection adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
21 maintain voltage regulation during a load transient. the voltage rating of the output capacitors must support the output voltage with sufficient design margin. the output voltage ripple (v out ) is a function of the output capacitors parameters: c o , esr co , esl co . (8) v out = i l1 esr co + v in ? vreg l1 esl co + i l1 8 f sw c o the type of output capacitors will determine which terms of equation 8 are dominant. for ceramic output capacitors, the esr co and esl co are virtually zero, so the output voltage ripple will be dominated by the third term of equation 8. (9) i l1 8 f sw c o vreg = to reduce the voltage ripple of a design using ceramic output capacitors, simply increase the total capacitance, reduce the inductor current ripple (i.e. increase the inductor value), or increase the switching frequency. the transient response of the regulator depends on the number and type of output capacitors. in general, minimizing the esr of the output capacitance will result in a better transient response. the esr can be minimized by simply adding more capacitors in parallel or by using higher quality capacitors. at the instant of a fast load transient (di/dt), the output voltage will change by the amount (10) vreg = i load esr co + di dt esl co after the load transient occurs, the output voltage will deviate from its nominal value for a short time. this time will depend on the system bandwidth, the output inductor value, and output capacitance. eventually, the error amplifier will bring the output voltage back to its nominal value. the speed at which the error amplifier will bring the output volt- age back to its setpoint will depend mainly on the closed-loop bandwidth of the system. a higher bandwidth usually results in a shorter time to return to the nominal voltage. however, it may be more difficult to obtain acceptable gain and phase margins in a a higher bandwidth system. selection of the compensation compo- nents (r z , c z , c p ) are discussed in more detail in the compensa- tion components section of this datasheet. ceramic input capacitors the ceramic input capacitor or capacitors must limit the voltage ripple at the vin pin to a relatively low voltage during maximum load. equation 11 can be used to calculate the minimum input capacitance, (11) c in i vreg(max) 0.25 0.9 f sw 50 mv where i vreg(max) is the maximum current from the pre-regulator, (12) i vreg(max) i linear + i aux + 20 ma where i linear is the sum of all internal linear regulators output currents, and i aux is any extra current drawn from the vreg output to power other devices external to the A4409. a good design should consider the dc-bias effect on a ceramic capacitor as the applied voltage approaches the rated value, the capacitance value decreases. an x7r type capacitor should be the primary choice due to its stability with both dc bias and tempera- ture variation. for all ceramic capacitors, the dc-bias effect is even more pronounced on smaller case sizes, so a good design will use the largest affordable case size. also for improved noise performance, it is recommended to add smaller-sized capacitors close to the A4409 vin pin and the d1 anode. use a 0.1 f, 0603 capacitor. buck-boost asynchronous diode (d1) the highest peak current in the asynchronous diode (d1) occurs during overload and is limited by the A4409. equation 5 can be used to calculate this current. the highest average current in the asynchronous diode occurs when v in is at its maximum, d boost = 0%, and d buck = mini- mum (10%), (13) i avg = 0.9 i vreg(max) where i vreg(max) is calculated using equation 12. boost mosfet (q1) the rms current in the boost mosfet (q1) occurs when v in is at its minimum and both the buck and boost operate at their maxi- mum duty cycles (approximately 64% and 58%, respectively), adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
22 (14) i q1(rms) = i b / b 2 d boost i b / b 12 + ( [ ) ] i peak ? 2 where i peak and i b/b are derived using equations 5 and 7, respectively. boost diode (d2) in buck mode, this diode will simply conduct the output current. however, in buck-boost mode, the peak currents in this diode may increase significantly. the A4409 limits the peak current to the value calculated using equation 5. the average current is simply the output current. pre-regulator compensation components (r z , c z , c p ) although the A4409 can operate in buck-boost mode at low input voltages, it can still be considered a buck converter when looking at the control loop. the following equations can be used to calcu- late the compensation components. first, the target crossover frequency for the final system must be selected. although the A4409 can switch at over 2 mhz, the crossover will be governed by the required phase mar gin. since a type ii compensation scheme is used, there are limits to the amount of phase that can be added. therefore, a crossover fre- quency, f c , of around 40 khz is selected. the total system phase will drop off at higher crossover frequencies. the r z selection is based on the gain required at the crossover frequency, and can be calculated by the following simplified equation: (15) 13.36 f c c o g m(power) g m(ea) r z = the series capacitor, c z , along with the resistor, r z , set the loca- tion of the compensation zero. this zero should be placed no lower than ? of the crossover frequency and should be kept to minimum value. equation 18 can be used to estimate this capaci- tor value. (16) c z > 4 2 r z f c determine if the second compensation capacitor (c p ) is required. it is required if the esr zero of the output capacitor is located at less than half of the switching frequency or the following rela- tionship is valid: (17) < 1 2 c o esr co f sw 2 if this is the case, then add the second compensation capacitor (c p ) to set the pole f p3 at the location of the esr zero. determine the c p value by the equation: (18) c p = c out esr r z finally, take a look at the combined bode plot of both the control- to-output and the compensated error amp see the red curves shown in figure 5. careful examination of this plot shows that the magnitude and phase of the entire system are simply the sum of the error amp response (blue) and the control-to-output response (green). as shown in figure 5, the bandwidth of this system (f c ) is 25.2 khz, the phase margin is 52.5 degrees, and the gain margin is 22 db. these values are theoretical; actual measured values may be different. some fine-tuning of the final compensation components may be necessary in the lab. -270 -225 -180 -135 -9 0 -4 5 0 45 90 13 5 18 0 -4 0 -3 0 -2 0 -1 0 0 10 20 30 40 50 60 10 01 00 01 0000 100000 100000 0 phase - gain -d b frequency -h z tota l gain c to o ga in e/a ga in tota l phas e c to o phase e/a phas e pm = 52.5 f c = 25.2 khz gm = 22 db figure 5 : bode plot of the complete system (red curve) r z = 6.19 k, c z = 4.7 nf, c p = 10 pf l o = 33 h, c o = 4 10 f ceramic linear regulators the two linear regulators only require a ceramic capacitor to ensure stable operation. the capacitor can be any value between 1 f and 22 f . a 2.2 f or 4.7 f capacitor per regulator is recommended. adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
23 internal bias (vcc) the internal bias voltage should be decoupled at the vcc pin using a 1 f , 25 v x7r ceramic capacitor . it is not recommended to use this pin as a source. signal pins (npor, enbat) the npor signal is an open drain output and requires an external pull-up resistor. it is recommended to pull npor up to the 5v0 rail, so when the A4409 is disabled, npor will not be high. the enbat is a high-voltage input pin. it does require a current- limiting resistor when connected to voltages greater than 8 v. there are limitations on this resistor value based on enba t sink current, enbat enable threshold, and input voltage operating conditions. minimum enbat resistor is 450 . if enba t must ensure A4409 is enabled down to the minimum operating voltage, then a resistor less than 3.37 k is recommended. watchdog (wd enn , wd in , wd adj ) the A4409 window watchdog circuit monitors an external clock applied to the wd in pin. this clock should be generated by the microcontroller or dsp. the time between rising edges of the clock must fall within an acceptable window or a watchdog fault will be generated. a watchdog fault will set npor for t wd(fault) (typically 2 ms). a watchdog fault will occur if the time between rising edges is either too short (a fast fault) or too long (a slow fault). the watchdog time window is programmable via the wd adj pin according to the following equations: r adj = 3.24 t wdto(slow) t wdto(fast) = t wdto(slow) / 8 where t wdto(slow) is the nominal watchdog timeout (in ms) and r adj is the required external resistor value (in k) from the wd adj pin to ground. typical watchdog operation under fast and slow fault conditions are shown in figure 7 and figure 8. the watchdog is enabled if two conditions are met: 1. the wd enn pin is a logic low, and 2. all regulators (5v0 and v5) have been above their undervolt - age thresholds for at least 30 ms typ (t wd(start) ). after startup, if no clock edges are detected at wd in for at least t wd(start) + t wdto(slow) , the A4409 will set npor low for t wd(fault) and reset its counters. this process will repeat until the system recovers and clock edges are applied to wd in . a timing diagram for the missing clock situation is shown in figure 9. figure 10 shows the wd fault signal during a fast clock fault. clk in 60 k wd osc window watchdog timer (wwdt) one shot t wd(fault) wd enn r adj = 64.9 k for t wdto(slow) = 20 ms wd enn wd in wd adj wd enn = 0 or open enables wd wd clk wd fault clk 1mhz wd start figure 6: watchdog block diagram adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
24 figure 7: window watchdog timer fast fault, t = wd in period * signal is internal to A4409 figure 8: window watchdog timer slow fault, t = wd in period * signal is internal to A4409 n wd s wd f n po r wd in s ta r t * f ault * t wd(start) 6 ms < t t wdto(fast) set to 5 ms (1 ms) t < 32 ms t < 4 ms t wdto(slow) set to 40 ms (8 ms) t wd(start) t wd(fault) n wd wd f n po r wd in start * f ault * 6 ms < t < 32 ms t t > 48 ms t wdto(fast) set to 5 ms (1 ms) t wdto(slow) set to 40 ms (8 ms) t wd(start) t wd(start) t wd(fault) adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
25 figure 9: window watchdog timer operation during slow clock fault, wd in stuck low or high * signal is internal to A4409 s w w d np or wd in s ta rt up d start * d faul t * t d(on)npor t wd(start) t wd(start) t wd(start) t wdto(slow ) t wdto(slow ) t wd(fault) t wd(fault) figure 10: window watchdog timer operation during fast clock fault * signal is internal to A4409 n s t wd s w d n po r wd in t ar tu p s tart * d faul t * t wd(start) t wd(start) t wd(start) t wd(start) t wd(fault) t wd(fault) t wd(fault) t wdto(fast ) t wdto(fast ) t wdto(fast ) t wdto(fast ) t wd(fault) t d(on)npor adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
26 pcb layout guidelines good layout of the power components and high di/dt loops is critical to proper operation of the A4409. it also helps to reduce emi generation. the first loop to consider is the buck regulator input loop. this consists of the input capacitors c3, c4, and c5, pins 2 and 18 of the A4409, and the diode d2. figure 11 shows this loop in red. c7 c6 c5 c4 c3 l1 d2 gnd gnd u1 11 92 0 18 3 enbat a 4409lp vinv cp cp 1c p2 lx 4.7 f 0.1 f 100 pf 2.2 f 1 f 2 d 18 3 v 2 figure 11 : buck high di/dt loop an example of how these components may be placed is shown below. ensure that these components and connecting traces are on the same side of the pcb. also ensure the enclosed area within the loop is as small as possible. the switch node trace connected to lx should be as short and as wide as possible to ensure the lowest possible impedance. figure 12 if the A4409 is configured as a buck-boost, then the boost output loop needs to be considered. this is made up of the boost mosfet q1, boost diode d7, and output capacitors c30 and c8. the boost switch node (l1, q1 drain, and d7 anode) should be as short and as wide as possible to ensure the lowest possible impedance. l1 d7 q1 gnd c30 c8 180 pf 10 f q c30 p figure 13 : boost output loop layout below shows the boost high di/dt loop. figure 14: boost high di/dt loop adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
27 also if configured for buck-boost mode, then care must be taken with the gate drive trace. the turn-on pulse is from c17 through A4409 pin 16 to q1 gate and source back to c17. the turn-off pulse is from q1 gate to A4409 pin 16 back to q1 source through the ground. figure 15 other sensitive nodes to keep small are the fset/sync to r3, the comp pin to c15 and c16, and wd adj pin to r adj . figure 16 adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
28 pin esd structures pin 8 v pgnd gnd cp1 cp2 vcp 8 v 40 v 40 v vin lx figure 17: vcc, comp, fset/sync, npor, wd enn , wd in , 5v0, v5, wd adj , vldo, vreg, lg figure 18: gnd, pgnd figure 19: vcp, cp1, cp2 figure 20: vin, lx enbat 40 v figure 21: enbat adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
29 package outline drawing for reference only ? not for tooling use (reference mo-153 act) not to scale dimensions in millimeters dimensions exclusive of mold ?ash, gate burrs, and dambar protrusions exact case and lead con?guration at supplier discretion within limits shown b a 1.20 max 0.05 nom 0.30 0.19 0.20 0.09 4o 0.60 nom 1.00 ref c seating plane c 0.10 20x 0.65 bsc 0.25 bsc 21 1 20 6.50 nom 4.40 nom 3.00 3.00 4.20 4.20 6.40 nom gauge plane seating plane a b 0.45 1.70 20 21 b 6.10 0.65 c exposed thermal pad (bottom surface) c pcb layout reference view nnnnnnn yyww lllllll standard branding reference view n = device part number = supplier emblem y= last two digits of year of manufacture w = we ek of manufacture l= lot number terminal #1 mark area reference land pattern layout (reference ipc7351 sop65p640x110-21m); all pads a minimum of 0.20 mm from all adjacent pads; adjust as necessary to meet application process requirements and pcb layout tolerances; when mounting on a multilayer pcb, thermal vias at the exposed thermal pad land can improve thermal dissipation (reference eia/jedec standard jesd51-5) figure 22: package lp, 20-pin etssop adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com
30 for the latest version of this document, visit our website: www.allegromicro.com revision history number date description C october 5, 2015 initial release 1 december 14, 2015 updated 5v0 undervoltage thresholds and hysteresis in electrical characteristics table (page 10). 2 march 31, 2016 corrected npor turn-off propagation delay test condition (page 10); corrected watchdog activation delay symbol (page 12); added wd adj pin shorted to ground or open circuit to summary of fault mode operation table (page 15); corrected figure 1 (page 16); corrected figure 3 (page 18); removed window watchdog timer operation during r adj fault figure (page 25); corrected pcb layout guidelines (page 27). 3 june 27, 2016 updated pin esd structures (page 28). 4 august 26, 2016 corrected figures 1, 2, and 3 (pages 16-18). copyright ?2016, allegro microsystems, llc allegro microsystems, llc reserves the right to make, from time to time, such departures from the detail specifications as may be required to permit improvements in the performance, reliability, or manufacturability of its products. before placing an order, the user is cautioned to verify that the information being relied upon is current. allegros products are not to be used in any devices or systems, including but not limited to life support devices or systems, in which a failure of allegros product can reasonably be expected to cause bodily harm. the information included herein is believed to be accurate and reliable. however, allegro microsystems, llc assumes no responsibility for its use; nor for any infringement of patents or other rights of third parties which may result from its use. adjustable frequency buck or buck-boost pre-regulator with 2 ldos, window watchdog timer, and npor A4409 allegro microsystems, llc 115 northeast cutoff worcester, massachusetts 01615-0036 u.s.a. 1.508.853.5000; www.allegromicro.com

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